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MPMB62D-68KX3 256MB PC-2700 DDR DIMM MPMB62D-68KX3 PC-2700 CL2.5 184pin DDR DIMM
32Mx64 DDR DIMM based on 16Mx8 DDR SDRAMs with SPD
DESCRIPTION
The MPMB62D-68KX3 is 32M bit x 64 Double Data Rate Synchronous Dynamic RAM high density memory module based on 128Mb DDR SDRAM respectively. The MPMB62D-68KX3 consists of sixteen CMOS 16M x 8 bit with 4 banks Double Data Rate Synchronous DRAMs in TinyBGA package and a 2K EEPROM in 8-Pin TSSOP package mounted on a 184pin glass-epoxy substrate. Two 0.1F decoupling capacitors are mounted on the printed circuit board in parallel for each DDR SDRAM. The MPMB62D-68KX3 is a Dual In- line Memory Module and is intended for mounting into 184pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of every clock cycle. Range of operating frequencies, programmable latencies and burst lengths allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.
FEATURES
* Performance range - 166MHz ( DDR333, CL2.5 ) * Double-data-rate architecture; two data transfers per clock cycle * Bi-directional data strobe (DQS) * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transition with CK transition * Auto & self refresh capability (4096 Cycles / 64ms) * Single 2.5V 0.2V power supply * Programmable Read latency 2, 2.5 (clock) * Programmable Burst length (2, 4, 8) * Programmable Burst type (Sequential & Interleave) * Edge aligned data output, center aligned data input * Serial presence detect with EEPROM * PCB : Height (1,181 mil), double sided component
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PIN CONFIGURATIONS (Front side/Back side)
Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
PIN NAME
Pin Name
A0 ~ A11 BA0 , BA1 DQ0 ~ DQ63 DQS0 ~ DQS7 CK0 ~ CK2 /CK0 ~ /CK2 CKE0 , CKE1 /CS0 , /CS1 /RAS /CAS /WE DM0 ~ DM7 VDD VDDQ VSS VREF VDDSPD SDA SCL SA0 ~ SA2 VDDID NC
Front
VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC NC VSS DQ8 DQ9 DQS1 VDDQ CK1 /CK1 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 *CB0 *CB1 VDD
Pin
47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92
Front
*DQS8 A0 *CB2 VSS *CB3 BA1 DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 VDDQ /ME DQ41 /CAS VSS DQS5 DQ42 DQ43 VDD NC DQ48 DQ49 VSS /CK2 CK2 VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS WP SDA SCL
Pin
93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138
Back
VSS DQ4 DQ5 VDDQ DM0 DQ6 DQ7 VSS NC NC *A13 VDDQ DQ12 DQ13 DM1 VDD DQ14 DQ15 CKE1 CDDQ *BA2 DQ20 *A12 VSS DQ21 A11 DM2 VDD DQ22 A8 DQ23 VSS A6 DQ28 DQ29 VDDQ DM3 A3 DQ30 VSS DQ31 *CB4 *CB5 VDDQ CK0 /CK0
Pin
139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184
Back
VSS *DM8 A10 *CB6 VDDQ *CB7 VSS DQ36 DQ37 VDD DM4 DQ38 DQ39 VSS DQ44 /RAS DQ45 CDDQ /CS0 /CS1 DM5 VSS DQ46 DQ47 NC VDDQ DQ52 DQ53 NC VDD DM6 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD
Function
Address input (Multiplexed) Select bank Address Data input/output Data Strobe input/output Clock input Clock input Clock enable input Chip select input Row address strobe Column address strobe Write enable Data-in mask Power supply (2.5V) Power supply for DQS (2.5V) Ground Power supply for reference Serial EEPROM power supply (2.5V~6V) Serial data I/O Serial clock Address in EEPROM VDD identification flag No connection
* These pins are not used in this module.
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FUNCTIONAL BLOCK DIAGRAM
CLK1 /CLK1 /CS1 /CS0 DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 22W x 10 /CLK /CS CLK DQS DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 120 W CLK2 /CLK2 /CLK /CS CLK DQS DM DQ0 DQ1 DQ2 U6 DQ3 DQ4 DQ5 DQ6 DQ7 /CLK /CS CLK DQS DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 120 W
/CLK /CS CLK DQS DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
22W x 10
U1
U9
/CLK /CS CLK DQS DM DQ0 DQ1 DQ2 U14 DQ3 DQ4 DQ5 DQ6 DQ7 /CLK /CS CLK DQS DM DQ0 DQ1 DQ2 U15 DQ3 DQ4 DQ5 DQ6 DQ7 /CLK /CS CLK DQS DM DQ0 DQ1 DQ2 U16 DQ3 DQ4 DQ5 DQ6 DQ7 120 W
DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
22W x 10
/CLK /CS CLK DQS DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
/CLK /CS CLK DQS DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
22W x 10
U2
U10
U7
DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 CLK0 /CLK0 DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
22W x 10
/CLK /CS CLK DQS DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
/CLK /CS CLK DQS DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS7 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
22W x 10
/CLK /CS CLK DQS DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
U3
U11
U8
22W x 10
/CLK /CS CLK DQS DM DQ0 DQ1 DQ2 U4 DQ3 DQ4 DQ5 DQ6 DQ7
/CLK /CS CLK DQS DM DQ0 DQ1 DQ2 U12 DQ3 DQ4 DQ5 DQ6 DQ7
DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
22W x 10
/CLK /CS CLK DQS DM DQ0 DQ1 DQ2 U5 DQ3 DQ4 DQ5 DQ6 DQ7
/CLK /CS CLK DQS DM DQ0 DQ1 DQ2 U13 DQ3 DQ4 DQ5 DQ6 DQ7
VDD One 0.1uF capacitor per each SDRAM VSS To SDRAM U1 ~ U16
A0 ~ A11,BA0,BA1 /RAS, /CAS, /WE CKE0 CKE1 VDDSPD Serial PD VDD SCL
SDRAM SDRAM SDRAM SDRAM
U1 ~ U16 U1 ~ U16 U1 ~ U8 U9 ~ U16
VREF One 0.1uF capacitor per each SDRAM VSS To SDRAM U1 ~ U8
SCL SDA
WP SDA A0 A1 A2
SA0 SA1 SA2
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ABSOLUTE MAXIMUM RATIINGS Parameter
Supply voltage relative to VSS I/O pins voltage relative to VSS Operating temperature Storage temperature Power dissipation Note: Permanent device damage may occur if
Symbol
VDD VIN, VOUT TA TSTG PD
Value
-1.0 ~ 3.6 -0.5 ~ 3.6 0 ~ +70 -55 ~ +125 16
Unit
V V C C W
"ABSOLUTE MAXIMUM RANTINGS" are
exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTIICS (SSTL_2 In/Out)
Recommended operating conditions (TA = 0 to 70C, VDD = +2.5V 0.2V)
Parameter
Supply Voltage I/O Reference voltage I/O Termination voltage (system) Input logic high voltage Input logic low voltage Input voltage level, CK and /CK inputs Input differential voltage, CK and /CK inputs Output high current (VOUT = 1.95V) Output low current (VOUT = 0.35V) Input leakage current Output leakage current
Symbol
VDD VREF VTT VIH(DC) VIL(DC) VIN(DC) VID(DC) IOH IOL II IOZ
Min
2.3 0.49xVDD VREF-0.04 VREF+0.15 -0.3 -0.3 0.3 16.8 -16.8 -16 -40
Max
2.7 0.51xVDD VREF+0.04 VDD +0.3 VREF-0.15 VDD +0.3 VDD +0.6 16 40
Unit
V V V V V V V mA mA A A
Note
1 2 3 3 4
5 6
Note : 1. VREF is expected to be equal to 0.5xVDD of the transmitting devices, and must track variations in the DC level of the same. Peak-to-peak noise on VREF, may not exceed 2% of the DC value. 2. VTT is not applied directly to the device. V is a system supply for signal termination TT resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 3. These parameters should be tested at the pin on actual components. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHz. 4. VID is the magnitude of the difference between the input level on CK and the input on /CK. 5. Any input 0V VIN VDD , VREF pin 0V VIN 1.35V, All other pins not under test = 0 V 6. 0V VOUT VDD , DQs are disabled.
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IDD CONDITIONS AND SPECIFICATIONS
Recommended operating conditions unless otherwise noted, TA = 0 to 70C, VDD = +2.5V 0.2V
Parameter / Condition
Operating current - One bank; Active-Precharge; tRC = tRC(Min); tCK = tCK(Min); DQ, DM and DQS inputs changing twice per clock cycle; Address and control inputs changing once per clock cycle Operating current - One bank; Active-Read-Precharge; Burst = 2; tRC = tRC(Min); tCK = tCK(Min); IOUT = 0 mA; Address and control inputs changing once per clock cycle Precharge power-down standby current; All banks idle; Power-down Mode; tCK = tCK(Min); CKE = LOW Idle standby current; /CS = HIGH; All banks idle; tCK = tCK(Min); CKE = HIGH; Address and control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM Active power-down standby current; One banks active; Power-down Mode; tCK = tCK(Min); CKE = LOW Active standby current; /CS = HIGH; CKE = HIGH; One bank; Active-Precharge; tRC = tRAS(Max); tCK = tCK(Min) ; DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once pre clock cycles Operating current; Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK(Min); IOUT = 0 mA Operating current; Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK(Min); DQ, DM and DQS inputs changing twice per clock cycle Auto refresh current; tRC = tRC(Min); distributed refresh Self refresh current; CKE 0.2V; External clock should be on Operating current; Four bank interleaving READs with BL = 4; Auto Precharge; tRC = tRC(min); tCK = tCK(min); Address and control inputs change only Active READ or WRITE commands
Symbol Max
Unit Note
IDD0
1080
mA
IDD1
1520
mA
IDD2P
520
mA
IDD2F
680
mA
IDD3P
560
mA
IDD3N
680
mA
IDD4R
1640
mA
IDD4W
1520
mA
IDD5 IDD6 IDD7
1960 80 2560
mA mA mA
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AC INPUT OPERATING CONDITIONS
Recommended operating conditions (TA = 0 to 70C, VDD = +2.5V 0.2V)
Parameter / Condition
Input logic high voltage Input logic low voltage Input differential voltage, CK and /CK inputs
Input crossing point voltage, CK and /CK inputs
Symbol
VIH(AC) VIL(AC) VID(DC) VIX(DC)
Min
VREF+0.31 0.7
Max
VREF-0.31 VDD +0.6
Unit Note
V V V V 1 1 2 3
0.5xVDD -0.2 0.5xVDD +0.2
Note : 1. These parameters should be tested at the pin on actual components. The AC and DC input specific ations are relative to a VREF envelop that has been bandwidth limited to 200MHz. 2. VID is the magnitude of the difference between the input level on CK and the input on /CK. 3. The value of VIX is expected to be equal 0.5xVDD of the transmitting device and must track variations in the DC level of the same.
AC OPERATING TEST CONDITIONS (TA = 0 to 70C, VDD = +2.5V 0.2V) Parameter Value
Input reference voltage for Clock Input signal maximum peak swing Input signal minimum slew rate Input Levels(VIH /VIL ) Input timing measurement reference level Output timing measurement reference level Output load condition 0.5xVDD 1.5 1.0 VREF+0.31 / VREF-0.31 VREF Vtt See Load Circuit
Unit
V V V V V V
Output Load Circuit (SSTL_2)
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AC TIMMING PARAMETERS AND SPECIFICATIONS (These AC characteristics were tested on the component) Parameter Symbol Min
Row cycle time Refresh row cycle time Row active time /RAS to /CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command Col. address to Col. address delay Clock cycle time CL = 2.0 CL = 2.5 tRC tRFC tRAS tRCD tRP tRRD tWR tCDLR tCCD tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPREH tDSS tDSH tDQSH tDQSL tDSC tIS tIH tHZ tLZ tSL(I) tSL(IO) tSL(O) tSLMR 60 72 42 18 18 12 2.5 1 1 7.5 6.0 0.45 0.45 -0.6 -0.7 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.75 0.75 tACmin - 400ps tACmin - 400ps 0.5 0.5 1.0 0.67 4.5 1.5 tACmax - 400ps tACmax - 400ps 1.1 12 12 0.55 0.55 +0.6 +0.7 +0.35 1.1 0.6 1.25
Max
70K
Unit Note
ns ns ns ns ns ns tCK tCK tCK ns tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK tCK tCK ns ns ps ps V/ns V/ns V/ns 6 7 10 6 6 2 5 5 5
Clock high level width Clock low level width DQS-out access time from CK, /CK Output data access time from CK, /CK Data strobe edge to output data edge Read Preamble Read Post amble CK to valid DQS-in DQS-in setup time DQS-in hold time DQS falling edge to CK rising-setup time DQS falling edge from CK rising-hold time DQS-in high level width DQS-in low level width DQS-in cycle time Address and Control Input setup time Address and Control Input hold time Data-out high impedance time from CK, /CK Data-out low impedance time from CK, /CK Input Slew Rate (for input only pins) Input Slew Rate (for I/O pins) Output Slew Rate (x8) Output Slew Rate Matching Ratio (rise to fall)
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Parameter
Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS DQ & DM input pulse width Power down exit time Exit self refresh to write command Exit self refresh to bank active command Exit self refresh to read command Refresh interval time Output DQS valid window Clock half period Data hold skew factor DQS write post amble time
Symbol
tMRD tDS tDH tDIPW tPDEX tXSW tXSA tXSR tREF tQH tHP tQHS tWPST
Min
12 0.45 0.45 1.75 10 95 75 200 15.6 tHPmin - tQHS tCLmin or tCHmin
Max
Unit Note
ns ns ns ns ns ns ns Cycle us ns ns 1 5 4 7,8,9 7,8,9
0.5 0.4 0.6
ns tCK 3
Note : 1. Maximum burst refresh of 8 2. The specific requirement is that DQS be valid (High or Low) on or before this CK edge. The case shown (DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. 3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. 4. A write command can be applie d with tRCD satisfied after this command. 5. For registered DINNs, tCL and tCH are 45% of the period including both the half period jitter (tJIT(HP)) of the PLL and the half period jitter due to cross talk (tJIT(crosstalk)) on the DIMM. 6. Input Setup/Hold Slew Rate Derating Input Setup/Hold Slew Rate (V/ns) tIS (ps) tIH (ps) 0.5 0.4 0.3 0 +50 +100 0 +50 +100
This derating table is used to increase tIS /tIH in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate.
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7. I/O Setup/Hold Slew Rate Derating I/O Setup/Hold Slew Rate (V/ns) 0.5 0.4 0.3
tIS (ps) 0 +75 +150
Tih (ps) 0 +75 +150
This derating table is used to increase tDS /tDH in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. 8. I/O Setup/Hold Plateau Derating I/O Input Level (mV) 280 tIS (ps) +50 tIH (ps) +50
This derating table is used to increase t S /tDH in the case where the input level is flat D below VREF 310mV for a duration of up to 2ns. 9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating Delta Rise/Fall Rate (ns/V) tIS (ps) 0 0.25 0.5 0 +50 +100 tIH (ps) 0 +50 +100
This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is collated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall Rate = -0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate. 10. This parameter is fir system simulation purpose. It is guaranteed by design.
Input/Output CAPACITANCE
(VDD = 2.5V, TA = 25C, f = 1MHz, VREF = 1.25V 100mV)
Pin
Input Capacitance: Command and Address Input Capacitance: /CS0, /CS1 Input Capacitance: CK0, /CK0, CK1, /CK1 Input Capacitance: CKE0, CKE1 Input/Output Capacitance: DQs, DQS
Symbol
CIN1 CIN2 CIN3 CIN4 CI/O
Min
65 42 42 27 10
Max
81 50 50 34 13
Unit
pF pF pF pF pF
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COMMAND TRUTH TABLE
Register Register Command Extended MRS Mode Register Set Auto Refresh Entry Self Refresh Exit CKEn-1 CKEn /CS /RAS /CAS /WE BA0,1 A10/AP A11,A9~A 0 H X L L L L OP code H X L L L L OP code H H L L L H X L L H H H L H X H X X X H X L L H H V Row address Column L address H X L H L H V (A0~A 9) H Column L address H X L H L L V (A0~A 9) H H H H L H L H H X H L X X L H L H L L H L X H L H L H L X V X X H X V X X H H H X V X X H X V X H L L X V X X H X V X H V X L H X X X Note 1, 2 1, 2 3 3 3 3 4 4 4 4, 6 7 5
Refresh
Bank Active & Row Address Read & Auto Precharge Disable Column Address Auto Precharge Enable Write & Auto Precharge Disable Column Address Auto Precharge Enable Burst Stop Bank Selection Precharge All Banks Active Power Down Entry Exit Entry Precharge Power Down Mode Exit DM No operation (NOP) : Not defined
X
X X
8 9 9
(V = Valid, X = Don't Care, H = Logic High, L = Logic Low) Note : 1. OP Code : Operand Code. A0 ~ A11 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2. EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatically precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A10 /AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9. This combination is not defined for any function, which means "No Operation (NOP)" in DDR SDRAM.
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PACKAGE DIMENSIONS
Units: Millimeter
1.00 2.20 3.00 133.35 131.35 128.95 127.35 1.00 2.20 3.00
B
30.00 17.80 10.00 2.30 1 6.35 64.77 77.47
U1
U2
U3
U4
U5
U6
U7
U8
4.0 0.1 4.0 0.1
53
92
A
1.27 0.05 49.53
B'
6.35
73.295 O2.5 0.1 R2.0 R2.0
60.055 O2.5 0.1 R2.0
93
145
184
U9
U10
U11
U12
U13
U14
U15
U16
R2.0
3.81 Max. 6.35 2.175
R 0.9 2.90 2.50 0.20 4.0 Min. 4.0 Min.
1.8 0.1
1.0 0.05
Detail A
1.27 0.1
Section B-B'
Tolerance : 0.15 unless otherwise specified The used device is 16Mx8 SDRAM TinyBGA
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SERIAL PRESENCE DETECT INFORMATION
Byte # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36~61 62 63 Function described # of bytes written into serial memory at module manufacturer Total # of bytes of SPD memory device Fundamental memory type # of row address on this assembly # of column address on this assembly # of module Rows on this assembly Data width of this assembly Data width of this assembly VDDQ and interface standard of this assembly DDR SDRAM cycle time from clock @CAS latency of 2.5 DDR SDRAM access time from clock @CAS latency of 2.5 DIMM configuration type (Non-parity , Parity , ECC ) Refresh rate & type Primary DDR SDRAM width Error checking DDR SDRAM data width Minimum clock delay for back-to-back random column address DDR SDRAM device attributes: Burst lengths supported DDR SDRAM device attributes: # of banks on each DDR SDRAM device DDR SDRAM device attributes: CAS Latency supported DDR SDRAM device attributes: CS Latency DDR SDRAM device attributes: WE Latency DDR SDRAM module attributes DDR SDRAM device attributes: General DDR SDRAM cycle time @CAS latency of 2 DDR SDRAM access time @CAS latency of 2 SDRAM cycle time @CAS latency of 1.5 SDRAM access time @CAS latency of 1.5 Minimum row precharge time (=tRP) Minimum row active to row active delay (tRRD) Minimum RAS to CAS delay (=tRCD) Minimum activate precharge time (=tRAS) Module Row density Command and Address signal input setup time Command and Address signal input hold time Data signal input setup time Data signal input hold time Superset information (maybe used in future) SPD data revision code Checksum for bytes 0 ~ 62 Function Supported 128 bytes 256 bytes (2K-bit) SDRAM DDR 12 10 2 Rows 64 bits SSTL 2.5V 6.0ns 0.7ns Non-parity , ECC 15.6us, support self refresh x8 N/A tCCD=1CLK 2,4,8 4 banks 2 &2.5 0 CLK 1 CLK Registered address & Control inputs and On-card DLL +/- 0.2 voltage tolerance 7.5ns 0.7ns 18ns 12ns 18ns 42ns 128MB 0.75ns 0.75ns 0.45ns 0.45ns Initial release Hex value 80h 08h 07h 0Ch 0Ah 02h 40h 00h 04h 60h 70h 00h 80h 08h 00h 01h 0Eh 04h 0Ch 01h 02h 20h 00h 75h 70h 00h 00h 48h 30h 48h 2Ah 20h 75h 75h 45h 45h 00h 00h E8h
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SERIAL PRESENCE DETECT INFORMATION
64 65 66 67 68~71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95~98 99~125 126 127 Manufacturer JEDEC ID code Manufacturer JEDEC ID code Manufacturer JEDEC ID code Manufacturer JEDEC ID code Manufacturer JEDEC ID code Manufacturing location Manufacturer part # (Memory module) Manufacturer part # (184 pin DIMM) Manufacturer part # (DDR 333) Manufacturer part # (Module density: 256MB) Manufacturer part # (Module density: 256MB) Manufacturer part # (Vdd = 2.5V) Manufacturer part # (DDR SDRAM) Manufacturer part # Manufacturer part # (DDR SDRAM type: 16Mb x 8) Manufacturer part # (DDR SDRAM type: 16Mb x 8) Manufacturer part # (Kingmax logo) Manufacturer part # (Kingmax logo) Manufacturer part # (CL=2.5) Manufacturer part # Manufacturer part # (option for die source) Manufacturer part # (option for module version) Manufacturer part # (option for die version) Manufacturer part # (reserve) Manufacturer revision code (reserve) Manufacturer revision code (reserve) Manufacturing date (Work Year) - BCD Manufacturing date (Work Week) - BCD (reserve) Assemble serial # -BCD (reserve) Manufacturer specific data (may be used in future) Intel specification for frequency Intel specification details for 100MHz support kingmax kingmax kingmax kingmax Hsin Chu (A) M P M B 6 2 D "-" 6 8 K X 3 "-" * * * 2002 Undefined Undefined 7Fh 7Fh 7Fh 25h 00h 41h 4Dh 50h 4Dh 42h 36h 32h 44h 2Dh 36h 38h 4Bh 58h 33h 2Dh * * * 00h 00h 00h 02h 00h 00h 00h 00h 00h FFh
128+ Unused storage locations
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March 2002 Rev: 1.1

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Price & Availability of MPMB62D-68KX3

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